
--------   Library and Packages   -----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--------   Interface or Entity   ------------
entity mux2to1_1bit is
	port (
		in0,in1,sel : in std_logic;
		outp : out std_logic
		  );
end mux2to1_1bit;
--------   Architecture or Body  ------------
architecture Behavioral of mux2to1_1bit is
	--signal in0, in1, sel, outp : std_logic;
begin
	--outp <= (in0 AND (NOT sel)) OR (in1 AND sel);
	outp <= (in0 AND (NOT sel)) OR (in1 AND sel) after 200 ps;
end Behavioral;

