library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_unsigned.ALL;

entity operators is
end operators;

architecture Behavioral of operators is

signal operand1, operand2 : std_logic_vector(3 downto 0) := X"F";	--for test
signal sum1, sum2, sum3 : std_logic_vector(4 downto 0);	-- one extra bit is necessary

begin

	sum1 <= ('0' & operand1) + ('0' & operand2);
	sum2 <= sum1 + 1; -- or '1'
	sum3 <= sum2 + '1';	-- overflow but no compiler ERROR

end Behavioral;

