library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_delays is
end AND_delays;
architecture Behavioral of AND_delays is
	signal x, y, z1, z2, z3, z4, z5 : std_logic;
begin
	Z1 <= X AND Y;
	Z2 <= transport (X and Y) after 10 ns;
	Z3 <= (X and Y) after 10 ns;
	Z4 <= inertial (X and Y) after 3 ns;
	Z5 <= reject 1 ns inertial (X and Y) after 5 ns;
-------------------------------------------------------	
	x <= '1';
	y <= '0', '1' after 5 ns, '0' after 7 ns,
	'1' after 10 ns, '0' after 14 ns, '1' after 15 ns,
	'0' after 30 ns;
end Behavioral;




--
--ENTITY My_Design IS
--	GENERIC ( 
--				 data_width : integer range 1 to 8 := 4;
--				 ...
--				 delay : time := 10 ns
--			  );
--	PORT ( ... );
--END ENTITY My_Design; -- END ENTITY -- END My_Design

