library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_Latch is
end SR_Latch;

architecture Behavioral of SR_Latch is

	signal s, r, q, q_not : std_logic := '0';
	
begin

	q <= '1' when s='1' else '0' when r='1';
	q_not <= '0' when s='1' else '1' when r='1';
	
	assert not (s='1' and r='1')
	report "S and R should not be '1' at a same time";
	-- severity error;
	
	s <= '1' after 1 ns, '0' after 2 ns, '1' after 3 ns;
	r <= '1' after 2 ns;
	
End Behavioral;
