.ALIASES
V_V1            V1(+=N00161 -=N00133 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS32@SOURCE.VSIN.Normal(chips)
D_D1            D1(1=N00161 2=N00186 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS69@DIODE.D1N4148.Normal(chips)
D_D2            D2(1=N00133 2=N00186 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS85@DIODE.D1N4148.Normal(chips)
D_D3            D3(1=0 2=N00161 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS101@DIODE.D1N4148.Normal(chips)
D_D4            D4(1=0 2=N00133 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS117@DIODE.D1N4148.Normal(chips)
R_R1            R1(1=0 2=N01173 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS222@ANALOG.R.Normal(chips)
C_C1            C1(1=0 2=N00186 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS341@ANALOG.C.Normal(chips)
R_R2            R2(1=N00186 2=N00648 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS675@ANALOG.R.Normal(chips)
D_D5            D5(1=0 2=N00648 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS1293@JDIODE.D02BZ4_7.Normal(chips)
Q_Q1            Q1(c=N00186 b=N00648 e=N01173 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS1442@PWRBJT.TIP31.Normal(chips)
Q_Q2            Q2(c=N02193 b=N02178 e=N02197 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2087@EBIPOLAR.BC107A.Normal(chips)
R_R3            R3(1=N02193 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2114@ANALOG.R.Normal(chips)
R_R4            R4(1=N02178 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2130@ANALOG.R.Normal(chips)
R_R5            R5(1=0 2=N02178 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2146@ANALOG.R.Normal(chips)
V_V2            V2(+=N02217 -=0 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2230@SOURCE.VDC.Normal(chips)
C_C2            C2(1=N02424 2=N02197 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2395@ANALOG.C.Normal(chips)
C_C3            C3(1=N06277 2=N02178 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2472@ANALOG.C.Normal(chips)
R_R7            R7(1=N025231 2=N02595 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2513@ANALOG.R.Normal(chips)
V_V3            V3(+=N02595 -=0 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2567@SOURCE.VSIN.Normal(chips)
C_C4            C4(1=N02193 2=N03346 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS2706@ANALOG.C.Normal(chips)
R_R10           R10(1=N03346 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3284@ANALOG.R.Normal(chips)
R_R9            R9(1=N03360 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3264@ANALOG.R.Normal(chips)
C_C5            C5(1=0 2=N03366 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3420@ANALOG.C.Normal(chips)
R_R11           R11(1=0 2=N03346 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3304@ANALOG.R.Normal(chips)
R_R12           R12(1=0 2=N03366 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3324@ANALOG.R.Normal(chips)
C_C6            C6(1=N03360 2=N04905 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3458@ANALOG.C.Normal(chips)
Q_Q3            Q3(c=N03360 b=N03346 e=N03366 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS3238@EBIPOLAR.BC107A.Normal(chips)
X_R14           R14(1=0 T=N02424 2=N02197 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS4450@BREAKOUT.POT.Normal(chips)
Q_Q4            Q4(c=N02217 b=N04905 e=N05299 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS5250@EBIPOLAR.BC107A.Normal(chips)
R_R15           R15(1=0 2=N05373 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS5283@ANALOG.R.Normal(chips)
I_I1            I1(+=N05299 -=0 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS5407@SOURCE.IDC.Normal(chips)
R_R16           R16(1=N04905 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS5494@ANALOG.R.Normal(chips)
C_C7            C7(1=N05299 2=N05373 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS5732@ANALOG.C.Normal(chips)
Q_Q5            Q5(c=N02217 b=N06730 e=N06277 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6209@EBIPOLAR.BC107A.Normal(chips)
R_R17           R17(1=N06666 2=N02217 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6236@ANALOG.R.Normal(chips)
I_I2            I2(+=N06277 -=0 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6261@SOURCE.IDC.Normal(chips)
C_C8            C8(1=N025231 2=N06730 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6423@ANALOG.C.Normal(chips)
R_R18           R18(1=0 2=N06666 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6650@ANALOG.R.Normal(chips)
R_R19           R19(1=N06666 2=N06730 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6705@ANALOG.R.Normal(chips)
C_C9            C9(1=N06666 2=N06277 ) CN @DCPOWERSUPPLYDESIGN.SCHEMATIC1(sch_1):INS6808@ANALOG.C.Normal(chips)
.ENDALIASES
